Interaction of Threads
Hi FolksIn the last write-up, I mentioned threads in simulation. Specifically, I said that the threads of a simulation can interact with each other. Well, what does that mean? Consider the Verilog code-snippet below – assign y = a + b; // continuous assignmentinitial begin // initial block$monitor(“@time %t -> a=%d, b=%d, y=%d”, $time,a,b,y); a …
Verilog Reg Datatype
/ Uncategorized / By admin Hi Folks, This is a longish read. I am covering reg and integer keywords of Verilog. These two topics are quite huge, but I have summarized the most used ways here. I suggest that you type and practice to ascertain yourselves as you read. If you have any questions, put them below in …
Verilog Assignments
/ Uncategorized / By admin Few examples on Verilog assignment If you refer to v2005 LRM, there are 2 interesting definitions, an extract of which is pasted below – 6.1 Continuous assignments Drives values onto nets, both vector and scalar; this assignment shall occur whenever the value of the right-hand side changes. An example is below: assign a …