Analog IO Layout

Job Description

• Hands on IO layout experience (from scratch) in most of technology nodes. Current emphasis is on 16nm Finfet or lower.
• Experience in solving DRC, LVS, ERC, EM, IR drop, Antenna issues etc. Extraction and analysis of layouts. Matching, Shielding techniques.
• Knowledge of using tools from Cadence (Virtuoso, PVS, Assura), Mentor (Calibre) etc
• Add-ons: Any scripting language (PERL, TCL ..)


6+ Years

Notice Period

No of Positions