Job Description

• Working experience in SOC or Subsystems designs for multiple projects
• Strong understanding of DFT methodologies and experience in standard DFT tools.
• Strong understanding on SMS architecture and verification expertise
• Familiarity with SoC style DFT architectures including multi-clock domain and low power design practices.
• Knowledge of DFT including Scan, MBIST
• Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
• Good experience Top-level clock/reset circuit design
• Knowledge on DFT simulations and debugging.


4 – 8 Years

Notice Period

No of Positions