Full chip Physical Verification

Job Description

• Work with floorplan and physical design engineers to drive physical verification convergence.
• Should be proficient in DRC and LVS analysis at advanced nodes like TSMC5 or below.
• Good knowledge in specific areas like Antenna, ESD, ERC, LUP will be preferred.
• Working knowledge on full chip phyV will be added advantage.
• Prior work experience on FullChip RDL like IO/PADRing routing will be preferred.
• Understanding on multi voltage regions will be preferred
• Expertise in Calibre and ICC2 tools.
• Scripting will be preferred.
• Scripting inside Calibre tool will be added asset.


4 – 10 Years

Notice Period

No of Positions