Physical Verification

Job Description

• Proficiency with physical verification tools such as Mentor Graphics Calibre, Synopsys IC Validator, and Cadence PVS.
• Strong understanding of semiconductor manufacturing processes and design rules.
• Experience with DRC, LVS, ERC, and PEX methodologies.
• Knowledge of advanced process nodes (e.g., 28nm, 14nm, 7nm, 5nm) and their specific verification challenges.
• Proficient in scripting languages such as Python, Perl, and TCL for automation purposes.
• Familiarity with version control systems (Git, SVN) and collaborative development workflows.


3 – 15 Years

Notice Period

No of Positions