RTL Design

• Proficiency in Verilog, VHDL, and System Verilog for RTL design.
• Experience with EDA tools for simulation (such as Synopsys VCS, Cadence Incisive), synthesis (such as Synopsys Design Compiler), and timing analysis (such as Prime Time).
• Strong understanding of digital design principles, including finite state machines (FSMs), pipelining, clock domain crossing (CDC), and low-power design techniques.
• Familiarity with RTL linting tools and methodologies for code quality and consistency.
• Experience with version control systems (Git, SVN) and collaborative development environments.