Soc Verification

Job Description

• Working experience in SOC/Sub-system level verification
• Strong understanding of SoC integration challenges at subsystem and full chip level
• Must have good knowledge on the verification flows. Excellent hands-on debug skills and problem-solving attitude.
• Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC
• Experience of working on Functional Verification, SoC Verification
• Good in programming: System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language, OVM/UVM Methodology knowledge and experience
• Must have good communication skills and the ability to work in a team environment.


4 – 15 Years

Notice Period

No of Positions