Job Description

• Proficiency with synthesis tools such as Synopsys Design Compiler, Cadence Genus, or Mentor Graphics Precision.
• Expertise in STA tools like Synopsys PrimeTime, Cadence Tempus, or similar.
• Strong understanding of digital design principles, including setup and hold timing, clock skew, and clock domain crossing (CDC).
• Experience with developing and maintaining synthesis and timing constraints (SDC files).
• Knowledge of low-power design techniques and their implementation during synthesis and STA.
• Strong scripting skills (TCL, Perl, Python) for automation of design flows.
• Familiarity with version control systems (Git, SVN) and collaborative development environments.


3 – 10 Years

Notice Period

No of Positions